1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device which supplies a prescribed output voltage according to a high power supply voltage in response to an internally generated signal.
2. Description of the Background Art
In order to drive a plasma display or the like, a high driving voltage (e.g., 100 V) is required and thus a high voltage semiconductor integrated circuit device (HVIC) is employed. A conventional structure of an output stage incorporated in such an HVIC is shown in FIG. 12. An equivalent circuit of the structure shown in FIG. 12 is the same as that of Embodiment 1 shown in FIG. 2, which will be described later. As shown in FIG. 2, this output stage is formed by a half bridge of an n channel D (Double Diffused) MOS transistor. A pnp bipolar transistor 107, resistor elements 109, 111 and an n channel DMOS transistor 113 in FIG. 2 are not shown in FIG. 12.
Referring to FIG. 12, an nxe2x88x92 type epitaxial layer 20 is formed on a pxe2x88x92 type semiconductor substrate 10. This epitaxial layer 20 is electrically isolated by p+ type isolating diffused regions 31 to 34 to be divided into island regions IR1, IR3, and IR4.
An n channel DMOS transistor 101 is formed in island region IR1. The source of this DMOS transistor 101 is formed by n+ type diffused regions 61 and 62. The drain of DMOS transistor 101 is formed by n type diffused region 81, epitaxial layer 20 and the like. The gate of DMOS transistor 101 is formed on a p type diffused region 51.
A Zener diode 105 is formed in island region IR3. The anode of Zener diode 105 is formed by a pxe2x88x92 type diffused region 71. The cathode of Zener diode 105 is formed by an n+ type diffused region 63.
An n channel DMOS transistor 103 is formed in island region IR4. The source of DMOS transistor 103 is formed by an n+ diffused region 64. The drain of DMOS transistor 103 is formed by an n+ type diffused region 66 and epitaxial layer 20. The gate electrode 93 of DMOS transistor 103 is formed on a p type diffused region 53.
A high power supply voltage Vdc of, for example, 100 V is supplied externally to this HVIC. In response to the signal generated in HVIC, output voltage Vout is changed between high power supply voltage Vdc and a ground (common) voltage.
A control signal generated by a logic circuit (not shown) in the HVIC is applied to the gates of DMOS transistors 103 and 113. When DMOS transistor 103 is turned on and DMOS transistor 113 is turned off, gate charge of DMOS transistor 101 is discharged and output terminal 104 is short-circuited to a ground terminal 106 through Zener diode 105, by DMOS transistor 103. As a result, output voltage Vout drops from high power supply voltage Vdc (e.g., 100 V) to ground voltage COM (0 V). Meanwhile, when DMOS transistor 103 is turned off and DMOS transistor 113 is turned on, a voltage is generated between two ends of a resistor element 109 by the power flowing to DMOS transistor 113. Accordingly, a bipolar transistor 107 is turned on so that gate voltage of DMOS transistor 101 is increased, and as a result, DMOS transistor 101 is turned on. Therefore, output voltage Vout is increased from ground voltage COM (0 V) to high power supply voltage Vdc (e.g., 100 V).
In the above-described conventional structure, there has been a problem that the chip size of this HVIC is made large since the area occupied by Zener diode 105 is large. The increase in the chip size owing to a single Zener diode 105 is small, but an HVIC generally includes many output stages, and thus the increase in the chip size owing to Zener diodes 105 cannot be ignored.
In addition, since the breakdown voltage of DMOS transistor 103 must be set high, the threshold voltage of DMOS transistor 103 tends to be high. Accordingly, DMOS transistor 103 cannot be turned on sufficiently with the voltage of the logical level. Thus, there has been a problem that on-resistance of DMOS transistor 103 is increased and the dropping rate of output voltage Vout from high power supply voltage Vdc to ground voltage COM is reduced.
Based upon the foregoing, it is an object of the present invention to provide a semiconductor device having a small size.
It is another object of the present invention to provide a semiconductor device in which the dropping rate of output voltage is fast.
According to one aspect of the present invention, a semiconductor device for supplying a prescribed output voltage according to high power supply voltage in response to an internally generated signal includes a first region, a first MOS transistor, a second region, a Zener diode and a second MOS transistor. The first region is formed at a semiconductor substrate. The first MOS transistor is formed at the first region, and has a drain receiving the high power supply voltage and a source supplying the output voltage. The second region is formed at the semiconductor substrate and is electrically isolated from the first region. The Zener diode is formed at the second region and has an anode connected to the source of the first MOS transistor and a cathode connected to the gate of the first MOS transistor. The second MOS transistor is formed at the second region and has a drain connected to the gate of the first MOS transistor and a source which is connected to the ground.
In this semiconductor device, the Zener diode and the second MOS transistor are formed at the same region so that the area occupied by the Zener diode is reduced. Accordingly, the size of this semiconductor device is made small.
According to another aspect of the present invention, a semiconductor device for supplying a prescribed output voltage according to a high power supply voltage in response to an internally generated signal includes a first MOS transistor, a bipolar transistor, and a second MOS transistor. The first MOS transistor has a drain receiving a high power supply voltage and a source supplying an output voltage. The bipolar transistor has a base connected to the gate of the first MOS transistor, an emitter connected to the source of the first MOS transistor, and a collector which is connected to the ground. The second MOS transistor has a drain connected to the gate of the first MOS transistor and a source which is connected to the ground.
In this semiconductor device, the current flowing to the second MOS transistor is amplified by the bipolar transistor so that the dropping rate of the output voltage is made faster. In addition, since the emitter and the base of the bipolar transistor function as a Zener diode, a high power supply voltage is applied between the gate and the source of the first MOS transistor and thus destruction of its gate film is prevented.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.